2024-03-28T11:07:17Zhttps://www.tdx.cat/oai/requestoai:www.tdx.cat:10803/803822017-08-29T11:15:32Zcom_10803_183col_10803_196
nam a 5i 4500
H.264
High definition
Video decoding
Parallel
SIMD
MPEG-2
Vector processors
Heterogeneous computing
Multicore
Computer architecture
Parallel programming
Parallel video decoding
[Barcelona] :
Universitat Politècnica de Catalunya,
2012
Accés lliure
http://hdl.handle.net/10803/80382
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Álvarez Mesa, Mauricio,
autor
1 recurs en línia (198 pàgines)
Tesi
Doctorat
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
2011
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Tesis i dissertacions electròniques
Ramírez Bellido, Alejandro,
supervisor acadèmic
Valero Cortés, Mateo,
supervisor acadèmic
TDX
Digital video is a popular technology used in many different applications. The quality of video, expressed in the spatial and temporal resolution, has been increasing continuously in the last years. In order to reduce the bitrate required for its storage and transmission, a new generation of video encoders and decoders (codecs) have been developed. The latest video codec standard, known as H.264/AVC, includes sophisticated compression tools that require more computing resources than any previous video codec. The combination of high quality video and the advanced compression tools found in H.264/AVC has resulted in a significant increase in the computational requirements of video decoding applications.
The main objective of this thesis is to provide the performance required for real-time operation of high quality video decoding using programmable architectures. Our solution has been the simultaneous exploitation of multiple levels of parallelism. On the one hand, video decoders have been modified in order to extract as much parallelism as possible. And, on the other hand, general purpose architectures has been enhanced for exploiting the type of parallelism that is present in video codec applications.
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