2024-03-28T19:02:23Zhttps://www.tdx.cat/oai/requestoai:www.tdx.cat:10803/60182017-08-29T11:03:04Zcom_10803_183col_10803_196
nam a 5i 4500
MT
CMP
harware priorities
thread prioritization
resource balancing
load balancing
powers
simultaneous multithreading
SMT
hardware-software codesign
performance characterization
software-controlled prioritization
Exploring coordinated software and hardware support for hardware resource allocation
[Barcelona] :
Universitat Politècnica de Catalunya,
2011
Accés lliure
http://hdl.handle.net/10803/6018
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AAMMDDs2011 sp ||||fsm||||0|| 0 eng|c
9788469404294
Figueiredo Boneti, Carlos Santieri de,
autor
Tesi
Doctorat
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
2009
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
Tesis i dissertacions electròniques
Cazorla Almeida, Francisco Javier,
supervisor acadèmic
Valero Cortés, Mateo,
supervisor acadèmic
Gioiosa, Roberto,
supervisor acadèmic
TDX
Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.<br/>This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.<br/>It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.<br/>In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
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