Now showing items 314-333 of 361

    Security architecture for Fog-To-Cloud continuum system 

    Kahvazadeh, Sarang (Date of defense: 2019-11-12)

    Nowadays, by increasing the number of connected devices to Internet rapidly, cloud computing cannot handle the real-time processing. Therefore, fog computing was emerged for providing data processing, filtering, aggregating, ...

    Security strategies in genomic files 

    Naro, Daniel (Date of defense: 2020-05-15)

    There are new mechanisms to sequence and process the genomic code, discovering thus diagnostic tools and treatments. The file for a sequenced genome can reach hundreds of gigabytes. Thus, for further studies, we need new ...

    Self-organized backpressure routing for the wireless mesh backhaul of small cells 

    Núñez Martínez, José (Date of defense: 2014-07-16)

    The ever increasing demand for wireless data services has given a starring role to dense small cell (SC) deployments for mobile networks, as increasing frequency re-use by reducing cell size has historically been the most ...

    Self-tuned parallel runtimes: a case of study for OpenMP 

    Duran González, Alejandro (Date of defense: 2008-10-22)

    In recent years parallel computing has become ubiquitous. Lead by the spread of commodity multicore processors, parallel programming is not anymore an obscure discipline only mastered by a few.<br/>Unfortunately, the amount ...

    Semantic resource management and interoperability between distributed computing platforms 

    Ejarque Artigas, Jorge (Date of defense: 2015-12-14)

    Distributed Computing is the paradigm where the application execution is distributed across different computers connected by a communication network. Distributed Computing platforms have evolved very fast during the las ...

    SIMD@OpenMP : a programming model approach to leverage SIMD features 

    Caballero de Gea, Diego Luis (Date of defense: 2015-12-11)

    SIMD instruction sets are a key feature in current general purpose and high performance architectures. SIMD instructions apply in parallel the same operation to a group of data, commonly known as vector. A single SIMD/vector ...

    Simulation methodologies for future large-scale parallel systems 

    Grass, Thomas (Date of defense: 2017-10-09)

    Since the early 2000s, computer systems have seen a transition from single-core to multi-core systems. While single-core systems included only one processor core on a chip, current multi-core processors include up to tens ...

    Síntesi d'alt nivell de circuits asíncrons 

    Badia Sala, Rosa Maria (Date of defense: 1994-07-20)

    (Català) A mesura que augmenta el nombre de transistors integrables en un xip, problemes com el desfasament del senyal de rellotge esdevenen cada cop més crítics. Altres avantatges com un consum més baix, una velocitat ...

    Smart and efficient sensor networks operation for 5G and beyond ecosystems 

    El Sayed, Ahmad Mohammad (Date of defense: 2024-01-30)

    (English) Sensor Networks (SN) will play an integral role in Beyond 5G (B5G) ecosystems, especially for highly-distributed use cases and services such as Digital Twins (DT). Thus, the underlying transport network needs to ...

    Smart hardware designs for probabilistically-analyzable processor architectures 

    Benedicte Illescas, Pedro (Date of defense: 2022-04-07)

    Future Critical Real-Time Embedded Systems (CRTES), like those is planes, cars or trains, require more and more guaranteed performance in order to satisfy the increasing performance demands of advanced complex software ...

    Smart memory management through locality analysis 

    Sánchez Navarro, Francisco Jesús (Date of defense: 2001-11-06)

    Las memorias caché fueron incorporadas en los microprocesadores ya desde los primeros tiempos, y representan la solución más común para tratar la diferencia de velocidad entre el procesador y la memoria. Sin embargo, muchos ...

    Soft error mitigation techniques for future chip multiprocessors 

    Upasani, Gaurang R (Date of defense: 2016-02-01)

    The sustained drive to downsize the transistors has reached a point where device sensitivity against transient faults due to neutron and alpha particle strikes a.k.a soft errors has moved to the forefront of concerns for ...

    Software caching techniques and hardware optimizations for on-chip local memories 

    Vujic, Nikola (Date of defense: 2012-06-05)

    Despite the fact that the most viable L1 memories in processors are caches, on-chip local memories have been a great topic of consideration lately. Local memories are an interesting design option due to their many benefits: ...

    Software diagnostics for autonomous safety-critical control-systems based on artificial intelligence 

    Fernández Muñoz, Javier (Date of defense: 2023-07-18)

    (English) Machine Learning (ML) systems allow the efficient implementation of functionalities that can be hard to program by traditional software due to the high spectrum of inputs that hinder the definition of a specific ...

    Specialization and reconfiguration of lightweight mobile processors for data-parallel applications 

    Duric, Milovan (Date of defense: 2016-01-26)

    The worldwide utilization of mobile devices makes the segment of low power mobile processors leading in the entire computer industry. Customers demand low-cost, high-performance and energy-efficient mobile devices, which ...

    Spectral analysis of executions of computer programs and its applications on performance analysis 

    Casas Guix, Marc (Date of defense: 2010-03-09)

    This work is motivated by the growing intricacy of high performance computing infrastructures. For example, supercomputer MareNostrum (installed in 2005 at BSC) has 10240 processors and currently there are machines with ...

    Speculative multithreaded processors 

    Marcuello Pascual, Pedro (Date of defense: 2003-07-22)

    En esta tesis se estudia el modelo de ejecución de los procesadores multithreaded especulativos así como los requisitos necesarios para su implementación. El modelo de ejecución se basa en la inserción de instrucciones de ...

    Speculative Vectorization for Superscalar Processors 

    Pajuelo González, Manuel A. (Manuel Alejandro) (Date of defense: 2005-11-24)

    Traditional vector architectures have been shown to be very effective in executing regular codes in which the compiler can detect data-level parallelism, i.e. repeating the same computation over different elements in the ...

    Statistical analysis and design of subthreshold operation memories 

    Rana, Manish (Date of defense: 2016-10-18)

    This thesis presents novel methods based on a combination of well-known statistical techniques for faster estimation of memory yield and their application in the design of energy-efficient subthreshold memories. The emergence ...

    Strategies for internet route control: past, present and future 

    Yannuzzi, Marcelo (Date of defense: 2007-12-19)

    Uno de los problemas más complejos en redes de computadores es el de proporcionar garantías de calidad y confiabilidad a las comunicaciones de datos entre entidades que se encuentran en dominios distintos. Esto se debe a ...